Offset cancellation (OC) is required in multi-stage amplifiers especially when there is a need to process small signals or extract AC signals superimposed on a large DC component (e.g. transimpedance amplifiers in optical communications). A commonly used topology uses an OC amplifier to force the DC component of the main amplifier output to zero. However, mismatch in an OC amplifier may cause the main amplifier to malfunction when the input signal is large and/or the input data rate is low, as some or all of the main amplifier stages limit/saturate.
Differential amplifier offset results from any phenomenon that causes a non-zero output without an input signal being applied to amplifier (amp) input. Typically, such errors are caused by device mismatch, noise, drift, etc. Some multi-stage amplifiers use a differential amp having an offset cancellation feedback loop between the last amplifier stage and the first amplifier stage. However, a large dc offset can often lead to saturation. Additionally, offset problems can intensify with each additional amp stage.
FIG. 1 is a schematic drawing of an offset cancellation scheme illustrating three differential amp stages labeled I, II and III (and serving as the main stages of an overall amplifier), respectively, connected together in series from the output of one to the input of another. Stage IV is shown connected to the output of the scheme which may, for instance, serve as a buffer amplifier. An offset cancellation loop is effected by providing an offset cancellation amplifier connected to and between the output of stage III and the input of stage I. An offset voltage, represented as Vos, is presented at an input of the offset cancellation amplifier OCA. With reference to the dynamic output cancellation scheme of FIG. 1, in connection with an input signal level increase, stage III may begin to saturate/limit. Once the stage III amplifier saturates, the gain of the OC loop, connected to an input of stage I, may drop.
Typically, reducing the value of an amplifier's imperfection as reflected to its input involves making the gain of the amplifier as large as practical. However, fixing component imperfections through transistor sizing mandates larger area and more power. Reducing the mismatch of an OC amplifier mandates more area and power, because the mismatch might decrease by 50% when the size of the OC amplifier increases, for instance, to 400%. This issue is even more pronounced when the input data-rate is low. As a result of these challenges, a better scheme may be useful to deal with offset problems in multi-stage amplifiers. As result, the input-referred offset increases.